This application is related to Japanese application No. 2001-049596 filed on Feb. 26, 2001, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly to a method for manufacturing a semiconductor device utilizing a silicidation process and a dummy gate process.
2. Description of the Prior Arts
When a gate length is reduced as a MOS transistor is made subminiaturized and made to have a high precision, there arises a problem of the deterioration in the performance of a transistor with the increase in wiring resistance of a gate electrode.
Conventional transistors utilize a dummy gate 64 as shown in FIGS. 3(a) to 3(e). Specifically, Japanese Unexamined Patent Application No. HE110-189966 discloses a technique for replacing the dummy gate electrode 64 with a metal gate electrode 74a after forming diffusion layers 68a and 68b. 
As shown in FIG. 3(a), a trench is firstly formed in a Si-substrate 61 by using an RIE technique, and then, an insulating film is embedded into the trench to form a device isolation layer 62. Subsequently, an SiO2 film 63 having a thickness of about 5 nm is formed on which a nitride film for the dummy gate electrode pattern 64 is then entirely deposited with a thickness of about 300 nm. The nitride film is patterned to form the dummy gate electrode pattern 64. An ion implantation is performed with the dummy gate pattern 64 as a mask for forming the diffusion layer 68b which serves as an LDD region. Thereafter, a sidewall spacer 67 is formed at the side wall of the dummy gate pattern 64. The ion implantation is performed with these dummy gate pattern 64 and sidewall spacer 67 as masks thereby forming the diffusion layer 68a. 
An CVD-SiO2 film 72 is deposited on the whole surface of the obtained Si-substrate 61, followed by a thermal treatment to cause an activation of the implanted ion thereby forming a source/drain region 68. Thereafter, the CVD-SiO2 film 72 is planarized by a CMP method as shown in FIG. 3(b) thereby exposing the surface of the nitride film serving as the dummy gate pattern 64.
Next, the exposed dummy gate pattern 64 is selectively removed as shown in FIG. 3(c) thereby exposing each surface of sidewall spacer 67 and SiO2 film 63. Then, a channel ion implantation is performed to a desired channel region with a resist film (not shown), CVD-SiO2 film 72 and the sidewall spacer 67 as masks.
Subsequently, the SiO2 film 63 is removed as shown in FIG. 3(d), a gate insulating film 73 and a metal film 74 are deposited onto the whole surface of the obtained Si-substrate 61.
Then, the whole surface of the obtained Si-substrate 61 is polished as shown in FIG. 3(e) with the CMP method thereby embedding the metal film 74 and the gate insulating film 73 into the trench from which the dummy gate pattern 64 has been removed, resulting in forming a gate electrode 74a are formed. An interlayer dielectric film 76 is deposited onto the whole surface of the obtained Si-substrate 61. Contact holes which extend to the full depth of the source/drain region 68 and the gate electrode 74a. An Al film is deposited onto the interlayer dielectric film 76 including the contact hole, and then, a patterning is executed to form a wiring 75.
The above-mentioned dummy gate process (replacement process of the dummy gate electrode with a metal gate electrode) can avoid the increase in wiring resistance of the gate electrode, deterioration at the edge portion of the gate insulating film or the like.
On the other hand, the diffusion layer represented by the source/drain region has a shallow junction depth with a sub-miniaturization, that causes an increase in wiring resistance. However, this problem has generally been solved by using a salicide technique. This salicide technique is to deposit a transition metal of Group VIII element such as Ti, Co, Ni or the like on the source/drain region of an active region and on polycrystalline silicon serving as the gate electrode, wherein a silicidation reaction is utilized between the silicon and the metal by a thermal treatment. It is one of the important techniques from the viewpoint of reducing the resistance of the diffusion layer of the source/drain region and the resistance of the gate electrode wiring.
Accordingly, this salicide technique is expected to be adapted to the dummy gate process.
For example, formed on a Si-substrate 41 having an isolation film 42 formed thereon are a dummy gate electrode 44a, source/drain region 48 and sidewall spacer 47 as shown in FIG. 4(a). Silicon nitride or polycrystalline silicon is used for the material of the dummy gate electrode 44a from the viewpoint of the simple use in the process and cost.
Subsequently, a metal film 50 that becomes a silicide material is deposited on the whole resultant surface as shown in FIG. 4(b).
Then, the obtained Si-substrate 41 is subject to a thermal treatment to cause the silicide reaction on the surface of the source/drain region 48, thereby forming a metal silicide layer 51. Thereafter, the unreacted metal film 50 is removed by an acid cleaning including sulfuric acid. The silicon nitride or polycrystalline silicon used as the material for the dummy gate electrode 44a is active with respect to the metal film 50 that becomes the silicide material, so that the dummy gate electrode 44a is silicide-reacted with the metal film 50 thereby forming a metal silicide layer 55 on the surface of the dummy gate electrode 44a. 
Next, an interlayer dielectric film 52 is deposited, followed by a planarization process with the CMP so as to expose the surface of the dummy gate electrode 44 as shown in FIG. 4(d).
Subsequently, the dummy gate electrode 44a is removed by a wet etching method.
However, the metal silicide layer 55 has a resistance to an etchant comprised of diluted hydrofluoric acid solution or the like, so that it is not completely removed and remains. Accordingly, there arises a problem that the metal silicide layer 55 remains or it impedes the removal of the dummy date electrode 44a as shown in FIG. 4(e), or the remaining metal silicide layer 55 impedes the deposition of the gate insulating film 53 and metal electrode film 54 on the area where the dummy gate electrode is removed as shown in FIG. 4(f).
The present invention provides a method for manufacturing a semiconductor device comprising:
(a) forming a dummy gate provided with a sidewall spacer at its side wall and an anti-silicidation film thereon on a semiconductor substrate, as well as forming a source/drain region on the surface of the semiconductor substrate;
(b) forming a metal film on the whole surface of the obtained semiconductor substrate, the resultant being subject to a silicide reaction to form a silicide layer only on the source/drain region;
(c) forming an interlayer dielectric film on the obtained substrate, the surface of the interlayer dielectric film being removed until the anti-silicidation film is exposed;
(d) removing the anti-silicidation film and the dummy gate to form a trench in the interlayer dielectric film; and
(e) laminating a gate insulating film and gate electrode material film in the trench, the gate insulating film and gate electrode material film being removed until the surface of the interlayer dielectric film is exposed to form a gate electrode and gate insulating film in the trench.
Accordingly, a method for manufacturing a semiconductor device of the present invention is capable of simply and assuredly adapting a silicide technique to a dummy gate process.